About the Position:

Our team is building key IPs in SSD controller, like NVMe  IP and flash controller IP. These IPs decide the functions and performance of SSD controller. Due to broad range of market targets, this team is required to make design flexible to support requirement from different market segments in a short period of time.  This position will expose to this design technic and as well all algorithms like interface with host and NAND and advanced LDPC error correcting technology.

This position in particular is focusing on SSD IP. You will  need to design UVM-based test environment to cover as many corners as possible. You will need to involve to come up with test plan, coverage check points, coverage script, test bench architecture, sequence agent design, scoreboard design … etc.

Responsibilities:

o   Develop next generation SSD controller utilizing advanced  digital technologies.

o   Writing Test suits for SSD controllers in UVM environment

o   UVM test bench development

o   Maintain and enhance UVM environment to support Advanced  SOC features

o   Debugging test benches

o   Perform functional verification of design on block and  system level.

o   Provide design documentation, description and information  to internal and external customers.

Minimum Qualifications:

o   Major in EE, CS or related

o    Familiar with Verilog and System-Verilog

o   Good knowledge on UVM methodology

Preferred Qualifications:

o   Good verbal and written English communication skills

o   Familiarity of ASIC design flow

o   Strong Programming Skills in Scripting/programming language  like PERL/Python, TCL & C/C++ is a plus.

o   Understanding of SSD controller architecture is a big  plus

o   Understanding of NVMe protocol is a big plus

o   SSD/NAND/NVMe/LDPC background knowledge is a big plus.